, we are a pioneering semiconductor startup company in Europe, dedicated to pushing the boundaries of technology with a focus on multi-core in-memory compute SoCs. As a member of our physical design team, you will play a pivotal role in contributing to our ongoing success and innovation.
As a Senior Silicon Physical Design Engineer at Axelera.ai
, you will be a key player in our physical design team, responsible for the development of Axelera's cutting-edge multi-core in-memory compute SoCs. You will leverage your extensive expertise in ASIC Physical Design, from RTL to GDS, to create physical design partitions that meet the highest standards in the industry. Your hands-on approach will encompass synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification. Collaboration with architecture and RTL teams will be crucial in ensuring the timely and successful realization of these physical partitions.
Essential Skills (Minimum Requirements):
Experience: You have a minimum of 10 years of experience in Physical Design, including a proven track record of implementing designs from RTL to GDS.
Communication and Teamwork: You excel in communication and teamwork, contributing effectively to diverse and inclusive teams.
Design Process: Your expertise includes synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. You understand constraints generation, STA, timing optimization, and timing closure.
EDA Tools: You have hands-on experience with EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
Clocking: You possess a proficient understanding of clock tree synthesis (CTS) and different clock-building techniques.
IP Integration: You have experience in IP integration, covering memories, IOs, embedded processors, double data rate, networking fabrics, and Analog IP.
Scripting: Proficiency in scripting languages such as Python, Tcl, or Perl.
Problem Solving: You demonstrate outstanding technical problem-solving and debugging abilities.
Language Skills: Fluent in English, both in speaking and writing.
Desirable Experience and Skills:
Top-Level Integration: Expertise in chip top-level integration, I/O ring design, ESD, and latch-up methodologies.
Collaboration: Experience interfacing with packaging teams and conducting chip-package-board co-simulations.
Influence: The ability to influence tools, flows, and overall design methodology.
Vendor Collaboration: Experience collaborating directly with tool vendors, driving resolution of tool issues and improvements.
Semiconductor Knowledge: Understanding of semiconductor device physics and transistor characteristics.
Multi-Domain Design: Experience with multi-clock, multi-power-domain design.
Continuous Integration: Knowledge of continuous integration methodology and architecting regression test-suites.
Process Management: Ability to set up processes and checks for receiving releases from IP vendors and providing IP releases to internal teams.
Autonomous Work: Capable of working autonomously and planning and performing research tasks.
Responsibility: You have a strong sense of responsibility and thrive in an environment where "Making the impossible possible" is the mindset.
What we offer:
This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.
An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.
Great! Apply directly via the button below. We are looking forward to receiving your application!